1. Field of the Invention
The present invention relates to a semiconductor device including a silicide layer and a manufacturing method thereof.
2. Description of the Related Art
In accordance with the reduction of an integrated circuit, a semiconductor device which forms an integrated circuit is required to have a lower contact resistance with a metal wiring and a lower resistance of an impurity region. Therefore, a technique in which a contact resistance or a resistance of an impurity region is reduced by forming a silicide layer in a semiconductor film is adopted in a semiconductor field (for example, Patent Document 1: Japanese Published Patent Application No. 2004-221115). When a resistance of a semiconductor film is reduced, an ON current of a semiconductor device is improved and a semiconductor device with a high characteristic can be manufactured.
On the other hand, when a silicide layer of a semiconductor is thickened, a sheet resistance is reduced; accordingly, it is predicted that an ON current becomes higher. However, it is reported in Non-Patent Document 1 (Non-Patent Document 1: OPTIMIZATION OF SERIES RESISTANCE IN SUB-0.2 μm SOI MOSFETs: Lisa T. Su et al., IEDM93, pp. 723-726, 1993) that when a silicide layer is actually formed to be thick, a resistance is increased and an ON current is decreased.